Analog Devices SHARC ADSP-21368 - Page 223

ADSP-21368 SHARC Processor Hardware Reference 4-21
Digital Audio/Digital Peripheral Interfaces
Figure 4-13. SRU_CLK1 Register
Figure 4-14. SRU_CLK2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1001111011110111
Reserved
Reset = 0x3DEF7BDE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0011110111101111
SRC2_CLK_OP_I
SRC1_CLK_OP_I
SRC2_CLK_IP_I
SRU_CLK1 (0x2431)
SRC1_CLK_OP_I
SRC1_CLK_IP_I
SRC0_CLK_OP_I
SRC0_CLK_IP_I
Sample Rate Converter 2
Clock Output Input
Sample Rate Converter 1
Clock Output Input
Sample Rate Converter 2
Clock Input Input
Sample Rate Converter 1
Clock Output Input
Sample Rate Converter 0
Clock Input Input
Sample Rate Converter 0
Clock Output Input
Sample Rate Converter 1
Clock Input Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1001111011110111
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0011110111101111
IDP2_CLK_I
Input Data Port 2
Clock Input
IDP0_CLK_I
Input Data Port 0
Clock Input
DIT_CLK_I
SRC3_CLK_IP_I
SRC3_CLK_OP_I
SRU_CLK2 (0x2432)
IDP0_CLK_I
Reset = 0x3DEF7BDE
IDP1_CLK_I
Input Data Port 1
Clock Input
Sample Rate Converter 3
Clock Input Input
SPDIF Transmitter
Clock Input
Sample Rate Converter 3
Clock Output Input
Input Data Port 0
Clock Input