ADSP-21368 SHARC Processor Hardware Reference 9-11
S/PDIF Transmitter/Receiver
DIT_HFCLK_I is the oversampling clock. This clock is divided down
according to the
FREQMULT bit in the transmitter control register to gener-
ate the bi-phase clock. It can also be selected from various sources since it
is routed through SRU1. The TX_CLK input to the S/PDIF transmitter is
controlled by the 5-bit clock routing (SRU1 group A) register field
SRU_CLK3[29:25] (DIT_HFCLK_I). This clock input can come from the
SPORTS, the PCG, external pins, or from the S/PDIF receiver. By default
TX_CLK is connected to LOGIC_LEVEL_LOW. For more information, see
“Group A Connections—Clock Signals” on page 4-19.
DIT_EXTSYNC_I is a clock input to the SPDIF transmitter and is con-
trolled by the 5-bit clock routing (SRU1 group A) register field
SRU_CLK4[19:15] (SPDIF_TX_EXT_SYNC). This clock can come from any of
20 external DAI pins. By default it is connected to LOGIC_LEVEL_LOW.
DIT_O is the bi-phase encoded data stream. It can be routed to any of the
external pins or to the S/PDIF receiver for loop-back testing through
SRU1. The SRU_PINx registers control this routing. For more information,
see “Group D Connections—Pin Signal Assignments” on page 4-36.
BLK_START indicates the last frame of the current block. This is high
for the entire duration of the frame. The BLK_START output can be routed
to any of the external pins controlled by the SRU_PINx registers. This can
also be connected to the DAI interrupts [31–22] using the SRU_MISCx reg-
isters. Use of this signal is optional.
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