ADSP-21368 SHARC Processor Hardware Reference 13-21
Precision Clock Generators
Listing 13-2. PCG Channel B Output Example
/* Register Definitions */
#define SRU_CLK4 0x2434
#define SRU_PIN0 0x2460
#define SRU_PBEN0 0x2478
#define PCG_CTLB0 0x24C2
#define PCG_CTLB1 0x24C3
#define PCG_PW 0x24C4
/* SRU Definitions */
#define PCG_CLKB_P 0x39
#define PCG_FSB_P 0x3B
#define PBEN_HIGH_Of 0x01
//Bit Positions
#define DAI_PB02 7
#define DAI_PBE02 6
#define PCG_PWB 16
/* Bit Definitions */
#define ENFSB 0x40000000
#define ENCLKB 0x80000000
/* Main code section */
.global _main;
.section/pm seg_pmco;
_main:
/* Route PCG Channel B clock to DAI Pin 1 via SRU */
/* Route PCG Channel B frame sync to DAI Pin 2 via SRU */
r0 = PCG_CLKB_P|(PCG_FSB_P<<DAI_PBE02);
dm(SRU_PIN0) = r0;