Programming Examples
13-22 ADSP-21368 SHARC Processor Hardware Reference
/* Enable DAI Pins 1 & 2 as outputs */
r0 = PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PB02);
dm(SRU_PBEN0) = r0;
r0 = (100<<PCG_PWB); /* PCG Channel B FS Pulse width = 100 */
dm(PCG_PW) = r0;
r2 = 1000; /* Define 20-bit Phase Shift */
r0 = (ENFSB|ENCLKB| /*Enable PCG Channel B Clock and FS*/
1000000); /* FS Divisor = 1000000 */
r1 = lshift r2 by -10;
/* Deposit the upper 10 bits of the Phase Shift in the */
/* correct position in PCG_CTLB0 (Bits 20-29) */
r1 = fdep r1 by 20:10;
r0 = r0 or r1; /* Phase Shift 19-10 = 0 */
dm(PCG_CTLB0) = r0;
r0 = (100000); /* Clk Divisor = 100000 */
/* Use CLKIN as clock source */
/* Deposit the lower 10 bits of the Phase Shift in the correct
position in PCG_CTLB1 (Bits 20-29) */
r1 = fdep r2 by 20:10;
r0 = r0 or r1; /* Phase Shift 9–0 = 0x3E8 */
dm(PCG_CTLB1) = r0;
_main.end: jump(pc,0);