ADSP-21368 SHARC Processor Hardware Reference 6-3
Serial Peripheral Interface Ports
Different CPUs or processors can take turns being master, or one master
may simultaneously shift data into multiple slaves (broadcast mode).
However, only one slave may drive its output to write data back to the
master at any given time. This must be enforced in broadcast mode, where
several slaves can be selected to receive data from the master, but only one
slave can be enabled to send data back to the master.
In a multimaster or multidevice environment where multiple processors
are connected through their SPI ports, all
MOSI pins are connected
together, all
MISO pins are connected together, as are the SPICLK pins. The
master’s
FLAGx pins connect to each of the slave SPI devices in the system
Figure 6-1. SPI Block Diagram
RX SHIFT REGISTER
RXSPI
RECEIVE
RE GISTE R
SPI INTERNAL
CLOCK
GENERATOR
TXSPI
TRANSMIT
REGISTER
32
MMSS
SPI IRQ OR
DMA REQUEST
TX SHIFT REGISTER
TXSR
RXSR
SPIINTERFACELOGIC
MOSI MISO SPICLK
FLAGX
DM DATA BUS
PM DATA BUS
I/0 DATA BUS
SPICTL
SPISTAT
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