ADSP-21368 SHARC Processor Hardware Reference A-15
Register Reference
Table A-4. External Port DMA Register Bit Descriptions
Bit Name Description
0DMAENDMA Enable.
0 = External port channel x DMA is disabled
1 = Enable External port DMA for channel x
1DMADRDMA Direction
0 = Write to internal memory (external reads)
1 = Read from internal memory (external writes)
Note: If delay line DMA is enabled then the DMADR bit doesn’t
have any effect. For delay line DMA, transfer direction depends
on the state of delay line transfers
2CHENEnable Chaining.
0 = Chaining disabled
1 = Chaining enabled
3DLENEnable Delay Line DMA. DLEN is applicable only if CHEN=1.
0 = Delay-line DMA disabled
1 = Delay-line DMA enabled
4CBENCircular Buffering Enable.
0 = Disables circular buffering with delay line DMA
1 = Enables circular buffering with delay line DMA
Circular Buffering can be used with normal DMA as well
5DFLSHFlush DMA FIFO (write-only).
6TFLSHFlush Tap List FIFO (write-only).
8–7 DFS DMA FIFO Status (read-only).
00 = FIFO empty
01 = FIFO partially full
11 = FIFO full
10 = Reserved
10–9 TFS Tap List FIFO Status (read-only).
00 = FIFO empty
01 = FIFO partially full
11 = FIFO full
10 = Reserved
11 DMAS DMA Transfer Status (read-only).
0 = DMA idle
1 = DMA in progress
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