SPORT Control Registers and Data Buffers
5-62 ADSP-21368 SHARC Processor Hardware Reference
This description applies only to DSP standard serial and multichannel
modes only.
Serial word endian select.
SPCTLx registers, bit 3 (LSBF). This bit selects
little endian words (LSB first, if set, = 1) or big endian words (MSB first,
if cleared, = 0). This description applies to DSP standard serial and multi-
channel modes only.
Serial word length select. SPCTLx registers, bits 8–4 (SLENx). These bits
select the word length in bits. Word sizes can be from 3 bits (SLEN = 2) to
32 bits (SLEN = 31). This bit applies to all operation modes.
Use this formula to calculate the value for SLEN:
SLEN = actual serial word length – 1
L
The SLEN bit cannot equal 0 or 1. I
2
S, and left-justified sample pair
word length is limited to 8-32 bits. DSP standard mode word
length varies from 3-32 bits.
16-bit to 32-bit word packing enable. SPCTLx registers, bit 9 (PACK). This
bit enables (if set, = 1) or disables (if cleared, = 0) 16- to 32-bit word pack-
ing. This bit applies to all operation modes.
Internal clock select. SPCTLx registers, bit 10 (ICLK). This bit selects the
internal (if set, = 1) or external (if cleared, = 0) transmit or receive clock.
This bit applies to DSP standard serial mode and multichannel modes.
Sport operation mode.
SPCTLx registers, bit 11 (OPMODE). This bit enables
I
2
S, left-justified sample pair, and packed I
2
S in multichannel modes if set
(= 1), or disables if cleared (= 0). This bit applies to all operation modes.
See Table 5-1 on page 5-11 and “Standard DSP Serial Mode” on
page 5-12.
Clock rising edge select. SPCTLx registers, bit 12 (CKRE). This bit selects
whether the SPORT uses the rising edge (if set, = 1) or falling edge (if
cleared, = 0) of the clock signal for sampling data and the frame sync. This
bit applies to DSP standard serial and multichannel modes only.
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