ADSP-21368 SHARC Processor Hardware Reference 5-61
Serial Ports
The following bits, listed in bit number order, control SPORT modes and
are part of the
SPCTLx (transmit and receive) control registers. Other bits
in the SPCTLx registers set up DMA and I/O processor-related SPORT fea-
tures. For information about configuring a specific operation mode, refer
to Table 5-1 on page 5-11 and “Standard DSP Serial Mode” on
page 5-12.
Serial port enable. SPCTLx registers, bits 0 and 24 (SPEN_A and SPEN_B).
These bits enable (if set, = 1) or disable (if cleared, = 0) the corresponding
SPORT channel A or B. Clearing these bits aborts any ongoing operation
and clears the status bits. The SPORTS are ready to transmit or receive
two serial clock cycles after enabling. This description applies to I
2
S,
left-justified sample pair, and DSP standard serial modes only.
Data type select. SPCTLx registers, bits 2–1 (DTYPE). These bits select the
companding and MSB data type formatting of serial words loaded into the
transmit and receive buffers. These bits applies to DSP standard serial and
multichannel modes only. The transmit shift register does not zero-fill or
sign-extend transmit data words; this only takes place for the receive shift
register.
For standard mode, selection of companding mode and MSB format are
exclusive:
00 = Right-justify; fill unused MSBs with 0s
01 = Right-justify; sign-extend into unused MSBs
10 = Compand using μ_law, (primary channels only)
11 = Compand using A_law, (primary channels only)
For multichannel mode, selection of companding mode and MSB format
are independent:
x0 = Right-justify; fill unused MSBs with 0s
x1 = Right-justify; sign-extend into unused MSBs
0x = Compand using μ_law
1x = Compand using A_law
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