ADSP-21368 SHARC Processor Hardware Reference 5-63
Serial Ports
Frame sync required select.
SPCTLx registers, bit 13 (FSR). This bit selects
whether the SPORT requires (if set, = 1) or does not require (if cleared,
= 0) a transfer frame sync. See “Frame Sync Options” on page 5-37 for
more details. This bit applies to DSP standard serial mode only.
Internal frame sync select. SPCTLx registers, bit 14 (IFS). This bit selects
whether the SPORT uses an internally-generated frame sync (if set, = 1) or
a frame sync from an external (if cleared, = 0) source. This bit is used for
standard DSP serial and multichannel modes only. This bit is referred as
IMFS in multichannel mode.
Low active frame sync select. SPCTLx registers, bit 16 (LFS). This bit
selects the logic level of the (transmit or receive) frame sync signals. This
bit selects an active low frame sync (if set, = 1) or active high frame sync (if
cleared, = 0). Active high is the default. This bit is called FRFS in I
2
S and
left-justified modes and LTDV/LMFS in multichannel mode.
Late frame sync select. SPCTLx registers, bit 17 (LAFS). This bit selects
when to generate the frame sync signal. This bit selects a late frame sync if
set (= 1) during the first bit of each data word. This bit selects an early
frame sync if cleared (= 0) during the serial clock cycle immediately pre-
ceding the first data bit. See “Frame Sync Options” on page 5-37 for more
details.
This bit applies to DSP standard serial mode only. This bit is also used to
select between I
2
S and left-justified sample pair modes. See Table 5-1 on
page 5-11 and “Standard DSP Serial Mode” on page 5-12 for more
information.
Serial port DMA enable. SPCTLx registers, bits 18 and 20 (SDEN_A and
SDEN_B). These bits enable (if set, = 1) or disable (if cleared, = 0) the
SPORT’s channel DMA. Bits 18 and 20 apply to all operating modes.
Serial port DMA chaining enable. SPCTLx registers, bits 19 and 21
(SCHEN_A and SCHEN_B). These bits enable (if set, = 1) or disable (if cleared,
= 0) SPORT’s channels A and B DMA chaining. Bits 19 and 21 apply to
all operating modes.
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