Operation Modes
5-4 ADSP-21368 SHARC Processor Hardware Reference
• In multichannel mode, support for packed I
2
S mode is new for the
ADSP-21367/8/9 and ADSP-2137x processors. However, it should
be noted that packed I
2
S mode is not identical to I
2
S mode in all
cases. For more information, see “Packed I2S Mode” on page 5-33.
• Even though SPORTs can operated independently in TDM mode,
compression and expansion logic is only available in SPORT0, 2,
4, and 6 and expansion logic is available only in SPORT1, 3, 5
and 7.
• The Frame sync error detection logic is added for the
ADSP-21367/8/9 and ADSP-2137x processors. It detects frame
syncs coming early where the frame sync arrives while transmis-
sion/reception of previous word is occurring. It does not detect
errors such as frame syncs arriving late. One dedicated error inter-
rupt is added which is shared by all sports.
The SPORTs are configurable for transferring data words between 3 and
32 bits in length, either most significant bit (MSB) first or least significant
bit (LSB) first. Words must be between 8 and 32 bits in length for I
2
S and
left-justified sample pair mode. Refer to “Data Word Formats” on
page 5-43 and the individual SPORTs operation mode sections for addi-
tional information.
Multichannel mode operation supports 128-channel TDM, described in
“Multichannel Operation” on page 5-25.
L
Receive comparison and two-dimensional DMA are not supported
in the ADSP-21367/8/9 and ADSP-2137x.
The
SPTRAN bit in the SPCTLx register affects the operation of the transmit
or the receive data paths. The data path includes the data buffers and the
shift registers. When
SPTRAN = 0, the primary and secondary RXSPxy data
buffers and receive shift registers are activated, and the transmit path is
disabled. When
SPTRAN = 1, the primary and secondary TXSPxy data buff-
ers and transmit shift registers are activated, and the receive path is
disabled.
To Next Page
Loading...
Need help?
General
