Analog Devices SHARC ADSP-21368 - Page 858

Index
I-2 ADSP-21368 SHARC Processor Hardware Reference
AMI bits
ACK pin enable (ACKEN), A-18
AMI enable (AMIEN), A-18
buffer flush (FLSH), A-19
bus hold cycle (HC), A-18
bus idle cycle (HC), A-19
disable packing (PKDIS), A-18
external bus data width (BW), A-18
most significant word first (MSWF),
A-18
predictive read disable (NO_OPT), A-19
read hold cycle (RHC), A-19
wait state enable (WS), A-18
AND breakpoints (ANDBKP) bit, A-178
AND, logical, 2-43, 14-3, A-178
architecture
I/O processor, 2-25
PWM, 8-2
SPDIF transmitter, 9-8
SPORT, 5-8
TWI controller, 12-3
asynchronous access mode (external
memory), 3-81
asynchronous memory interface. See AMI
asynchronous serial communications
(UART), 11-2
audience, intended, xxxi
autobaud detection, 11-1
B
bandwidth in the I/O processor, 2-12
bank
internal memory, 3-33
SDRAM address mapping, 3-51 to 3-57
bank activate command, 3-31
bank column address width, setting, 3-42
baud rate, 6-30, 14-49
setting, 2-43, 6-10
baud rate (continued)
SPIBAUD (serial peripheral interface
baud rate) register, 6-5, A-60
UART, 11-4, 11-5, 11-12
beginning and ending an SPI transfer, 6-29
BHD (buffer hang disable) bit, 5-64, 5-69
BI (break interrupt) bit, 11-4
bidirectional connections through the
signal routing unit, 4-13
bidirectional functions (transmit, receive),
5-1
biphase
encoded audio stream, 9-10
encoded data register (SPDIF_RX_I),
9-18
encoding, 9-11
bits
See also peripheral specific bits
circular buffer x overflow interrupt
(CBxI), B-17, B-21, B-25
emulator lower priority interrupt
(EMUI), B-14, B-18, B-19, B-21,
B-23, B-26
timer expired high priority (TMZHI),
B-15, B-19, B-23
timer expired low priority (TMZLI),
B-17, B-21, B-25
block diagram
I/O processor, 2-25
input data port, 7-2
PWM, 8-2
SPDIF transmitter, 9-8
SPORT, 5-8
SRC,
10-9
TWI controller, 12-3
boolean operator
AND, 2-43, 14-3, A-178
OR, 7-30, 9-24, A-175, A-177, A-178
boot memory select (BMS
) pin, 3-30,
14-39