SPI Transfer Formats
6-30 ADSP-21368 SHARC Processor Hardware Reference
The
RXS bit defines when the receive buffer can be read. The TXS bit
defines when the transmit buffer can be filled. The end of a single word
transfer occurs when the RXS bit is set. This indicates that a new word has
been received and latched into the receive buffer, RXSPI. The RXS bit is set
shortly after the last sampling edge of SPICLK. The latency is typically a
few core clock cycles and is independent of CPHASE, TIMOD, and the baud
rate. If configured to generate an interrupt when RXSPI is full
(TIMOD = 00), the interrupt becomes active one core clock cycle after RXS is
set. When not relying on this interrupt, the end of a transfer can be
detected by polling the RXS bit.
To maintain software compatibility with other SPI devices, the SPI trans-
fer finished bit (SPIF) is also available for polling. This bit may have
slightly different behavior from that of other commercially available
devices. For a slave device, SPIF is set at the same time as RXS. For a master
device, SPIF is set one-half of the SPICLK period after the last SPICLK edge,
regardless of CPHASE or CLKPL.
The baud rate determines when the SPIF bit is set. In general, when
(SPIBAUD < 4) SPIF is set after RXS. The SPIF bit is set before the RXS bit is
set, and consequently before new data has been latched into the RXSPI
buffer. Therefore, for SPIBAUD = 2 or SPIBAUD = 3, the processor must wait
for the RXS bit to be set (after SPIF is set) before reading the RXSPI buffer.
For larger SPIBAUD settings (SPIBAUD > 4), RXS is set before SPIF is set.
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