ADSP-21368 SHARC Processor Hardware Reference 14-3
System Design
The processors also include the multiplexers for
FLAG0–3 pins. The
FLAG0–2 pins can act as core FLAGS0–2 or IRQ0–2, and the FLAG3 pin can act
as a core FLAG3 or as the TMREXPEN signal of the system timer.
Table 14-1 on page 14-7 shows the SYSCTL register bit settings for the dif-
ferent data pin functions, and Figure 14-1 and Figure 14-2 show the
block diagrams of data pin multiplexing in the ADSP-21367/8/9 and
ADSP-2137x processors respectively. Note that:
• In the PDAP control register (IDP_PP_CTL), the IDP_EP_SELECT bit
(bit 26) is the logical AND of the IDP_PDAP_EN bit (bit 31). When
IDP_EP_SELECT is set (= 1), the data bits are read from DATA31–12
and the control signals come from DATA11-8. When IDP_EP_SELECT
is cleared (= 0), the data bits are read from DAI_P20–1. When
IDP_EP_SELECT is set to 1, the PDAP can be operated through data
pins alone (data and controls are completely routed through data
pins). For bit descriptions, see “Parallel Data Acquisition Port
Control Register (IDP_PP_CTL)” on page A-74.
• The PDAP, PWM, and memory-to-memory (MTM_DATA) signals can
be mapped only to the upper bits of the data pins. Therefore, they
can be used even when 8- or 16-bit external SRAM is used.
• The FLAGS and PWM can be mapped (in groups of four) to any
of upper 16 data pins. The FLAGS alone can be mapped to any of
the 32 data pins.
• For PDAP mode, the SYSCTL register must be explicitly pro-
grammed to put DATA pins in PDAP mode. For bit descriptions, see
“System Control Register (SYSCTL)” on page A-5.
• By default, after reset, all data pins are in external memory mode
and the FLAG0-3 pins are in FLAGS mode.
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