ADSP-21368 SHARC Processor Hardware Reference B-25
Interrupts
15 SP3I SPORT 3 Interrupt. When the processor is servicing another interrupt,
this bit indicates if the SP3I interrupt is unmasked (if set, = 1), or
masked (if cleared, = 0). An SP3I interrupt occurs two cycles after the
last bit of an input/output serial word is latched into/from
RXSP3A/TXSP3A, or RXSP3B/TXSP3B.
16 SP5I SPORT 5 Interrupt. When the processor is servicing another interrupt,
this bit indicates if the SP5I interrupt is unmasked (if set, = 1), or
masked (if cleared, = 0). An SP5I interrupt occurs two cycles after the
last bit of an input/output serial word is latched into/from
RXSP5A/TXSP5A, RXSP5B/TXSP5B.
17 Reserved
18 P15I Programmable Interrupt 15 (MTMDMA Interrupt).
19 Reserved
20 CB7I DAG1 Circular Buffer 7 Overflow Interrupt. When the processor is
servicing another interrupt, this bit indicates if the CB7I interrupt is
unmasked (if set, = 1), or masked (if cleared, = 0). A circular buffer
overflow occurs when the DAG circular buffering operation increments
the I register past the end of the buffer.
21 CB15I DAG2 Circular Buffer 15 Overflow Interrupt. When the processor is
servicing another interrupt, this bit indicates if the CB15I interrupt is
unmasked (if set, = 1), or masked (if cleared, = 0). A circular buffer
overflow occurs when the DAG circular buffering operation increments
the I register past the end of the buffer.
22 TMZLI Timer Expired (Low Priority) Interrupt. When the processor is servic-
ing another interrupt, this bit indicates if the TMZLI interrupt is
unmasked (if set, = 1), or masked (if cleared, = 0). For more informa-
tion, see “TMZHI” on page B-15.
23 FIXI Fixed-Point Overflow Interrupt. When the processor is servicing
another interrupt, this bit indicates if the FIXI interrupt is unmasked
(if set, = 1), or the FIXI interrupt is masked (if cleared, = 0).
24 FLTOI Floating-Point Overflow Interrupt. When the processor is servicing
another interrupt, this bit indicates if the FLTOI interrupt is unmasked
(if set, = 1), or masked (if cleared, = 0).
Table B-7. IMASKP Register Bit Descriptions (Cont’d)
Bit Name Description
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