Analog Devices SHARC ADSP-21368 - Page 859

ADSP-21368 SHARC Processor Hardware Reference I-3
Index
booting
boot kernel, 14-37
BOOT_CFGx (boot source
configuration) pins, 14-38
bootstrap loading, 14-37
from SPI flash, 14-42
SPI port, 14-42
broadcast mode, 6-3, 6-8
buffer, 2-39, 5-7
chain pointer load sequence, 2-38
circular, 2-37
DAI pin, 4-3
data buffer registers, 2-25
data, addressing, 2-29
external, 3-75
external register, 3-45
flash (AMI boot mode), 14-39
output example, 4-12
pin, defined, example, 4-10
SPORT data, 5-1
SPORT DMA, 5-15
SPORT transmit and receive, 5-61
SPORTs, activating, 5-4
system example (multiple SDRAM),
3-46, 3-47
UART restriction, 2-47
buffer hang disable (BHD) bit, 5-64, 5-69,
A-39
burst length, in SDRAM, 3-32
burst stop command (SDRAM), 3-32
burst type definition, 3-32
bus lock (BUSLK) bit, 3-88, 3-92
bus lock and semaphores, 3-92
bus master (Bm) condition, 3-82, 3-93
bus master count (BCNT) register, 3-87
bus master max time-out (BMAX) register,
3-87
bus master, current (CRBMx) bit, 3-93,
A-9
bus request BRx
signal, 3-85
bus request, shared memory (BRx
) pins,
3-81, 3-92
bus synchronized (BSYN) bit, 3-89, 3-93,
A-9
bus transition cycle (BTC), 3-82
buses
arbitration, 2-20, 3-79, 3-82
bus lock, 3-92
bus lock (BUSLK) bit, A-8
bus master
timeout, 3-87
conflict resolution ratio, 3-25
contention, 2-20, 6-17, A-3
errors in, 3-71
external bus data width (BW) bit, A-18
force sync of shared memory bus
(FSYNC) bit, A-8
granting, 2-21, 6-20
hold cycle bit, A-18
I/O address (IOA), 2-29
I/O data (IOD), 2-19, 2-20, 6-17
I/O processor (IOP), 2-25, 5-44
I
2
S and, 5-20
idle cycle bit, A-19
master, 3-84
master timeout, 3-87
serial, 5-27
shared memory bus arbitration, 3-79
slave, 3-84
stalls on, 14-54
synchronization, 3-88
TDM method over serial, 5-27
bypass as a one-shot (strobe pulse), 13-13
C
capacitors
bypass, 14-35
decoupling, 14-35