ADSP-21368 SHARC Processor Hardware Reference 3-45
External Port
Force auto-refresh.
Force AR bit 20. When set (=1), forces auto-refresh.
When cleared (=0), has no effect. Note that when SDORF bit is set, setting
this bit causes Force AR to have no effect.
Force precharge. Force PC bit 21. When set (=1), forces precharge. When
cleared (=0), has no effect.
Force load mode register. Force LMR bit 22. If set (=1), when SDRAMs
are in a precharged state, a mode register write to SDRAMs is initiated
immediately. This is in contrast to the normal load mode register set
which requires some delay. This command performs a precharge all (if not
precharged already) followed by a mode register write (ADSP-2137x pro-
cessors only).
External register buffer pipeline option. SDBUF bit 23. Enables, if set (=1),
or disables, if cleared (=0), external buffer timing. When buffered
SDRAM modules or discrete register buffers are used to drive the SDRAM
control inputs, SDBUF should be set to 1. This adds a cycle of data buffer-
ing to read and write accesses. An example single processor system is
shown in Figure 3-7.
When no buffering is required, the example shown in Figure 3-6 can be
used.
SDRAM tRCD parameter setting. SDTRCD bits 26–24. Sets the required
delay (in terms of
SDCLK) between a bank activate command and the start
of the first read or write command.
SDRCD
t
RCDmin
t
SDCLK
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