Analog Devices SHARC ADSP-21368 - Page 860

Index
I-4 ADSP-21368 SHARC Processor Hardware Reference
CAS latency
bit (SDCL), A-22
definition, 3-32
setting, 3-40
catastrophic interrupts, 4-65
CBR (CAS before RAS) definition, 3-33
CBxI (circular buffer x overflow interrupt)
bit, B-17, B-21, B-25
center-aligned paired PWM
double-update mode, 8-11
single-update mode, 8-9
chain loading sequence, 2-18
chain pointer registers, 2-15, 2-16
defined, 2-27
DMA buffer, 5-76
SPI address in memory (CPSPI), 2-42,
6-16, 6-19
SPORT address in memory (CPSPx),
A-51
SPORTs, 5-77, 5-81, A-51
starting address, 2-27
chained DMA, 2-14
chaining, 2-13 to 2-42
chain insertion mode, 2-41
chained DMA enable (SCHEN_A and
SCHEN_B) bit, 5-22, 5-63, 5-75,
5-81, A-38
chained DMA sequences, 2-14
DMA, 2-13 to 2-42, 6-27
in serial ports, 5-81, A-38
SPI chained DMA enable (SPICHEN)
bit, 6-19
chaining requests, multiple, 2-18
changing SPI configuration, 6-21
channel
buffer, 2-7
DMA, 2-9, 2-12, 2-13
interrupt, 2-8
priority scheme, 2-2
status,
2-7, 2-13
channel B transmit status register
(SPDIF_TX_CHSTB), A-90, A-91
channel double frequencey mode, single,
9-8
channel mode (SPDIF), two, 9-8
channel number, encoded, 7-19
channel selection registers, 5-31
channels, input data port, 7-1
circular, 2-39
circular buffering, 2-37, 2-39
CLKOUT (clock output) signal, 14-12
clock A source (CLKASOURCE) bit,
A-157
clock divisor (CLKDIV) bits, A-44
clock input (CLKIN) pin, 4-72, 13-2,
13-20, 14-20
clock rising edge select (CKRE) bit, 5-62
clocks and system clocking
CLKOUT and CCLK clock generation,
14-30
clock and frame sync frequencies (DIVx)
registers, 5-69, A-44
clock distribution, 14-34
clock divisor (CLKDIV) bit, A-44
clock input (CLKIN) pin, 14-13, 14-20
clock output enable, 13-3
clock polarity (CLKPL) bit, A-55
clock ratio, 14-31
clock relationships, 14-31
clock rising edge select (CKRE) bit, 5-62,
A-38
clock signal options, 5-71
clocking edge selection, 7-12
core clock ratio, 14-31
definitions, 14-31
determining switching frequencies,
14-29
external master clock, 14-21
frame sync bypass mode, 13-6