ADSP-21368 SHARC Processor Hardware Reference I-5
Index
clocks and system clocking (continued)
frame sync bypass mode, direct bypass,
13-6
frame sync bypass mode, one shot, 13-6
internal clock select (ICLK) bit, A-37
jitter, 14-33
master clock (MCLK), 10-8, 13-18
output control (ENCLKA/B) bits, 13-3
precision clock generator registers, 13-3,
13-7
SDRAM controller, 3-37
serial port count (SPCNTx) registers,
A-45
source select (MSTR) bit, A-37
SPI clock phase select (CPHASE) bit,
A-55
SPI clock rate, 6-5
code select (CSEL) bit, 3-82
column, row and bank address mapping
(32-bit), 3-53
commands
auto-refresh, 3-70
bank activate, 3-31, 3-65
booting, 14-48, 14-51
burst stop, 3-32
load mode register, 3-64
NOP, 3-72
precharge, 3-34, 3-66
read/write, 3-67, 14-50
SDRAM read, A-22
self-refresh, 3-70
SPI master, 6-20
SPI transfer, 6-10
compand data in place, 5-48
companding (compressing/expanding), 5-3
conditioning input signals, 14-32
configurable channels, digital audio
interface interrupts, A-112
configuring frame sync signals, 5-6
connecting peripherals, 4-8
connections
group A, DAI, clock signals, 4-19
group A, DPI, input routing signals,
4-52
group B, DAI data signals, 4-25
group B, DPI, pin assignment signals,
4-56
group C, DAI, frame sync signals, 4-31
group C, DPI, pin enable signals, 4-64
group D, DAI, pin signal assignments,
4-36
group E, DAI, miscellaneous signals,
4-43
group F, DAI, pin enable signals, 4-47
controller, SDRAM,
3-30
conventions, manual, xliii
core access to IOP registers, 2-3
core address mapping, 3-52
core clock cycle, 6-30
core PLL, 13-2
core transmit/receive operations, 6-13
count registers
DMA sport (CSPx), A-51
DMA, defined, 2-27
DMA, restrictions, 2-31
IDP DMA (IDP_DMA_Cx), 7-28
CPSPI (SPI chain pointer) registers, A-65
crossover mode, PWM, 8-16
crosstalk, reducing, 14-34
CSPI, CSPIB (SPI DMA word count)
registers, A-64
CSPx (peripheral DMA counter) registers,
2-31, A-51
customer support, xxxv
D
DAI
buffers, pin, 4-3
channel number, encoded, 7-19
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