Analog Devices SHARC ADSP-21368 - Page 862

Index
I-6 ADSP-21368 SHARC Processor Hardware Reference
DAI (continued)
clock routing control registers (group A),
4-19
configurable interrupts, A-112
configuration macro, 4-77
connecting peripherals with, 4-8
default configuration, 4-18
general-purpose (GPIO) and flags, 4-64
interrupt controller, 4-65 to 4-71
interrupt controller registers, A-112
interrupts, 4-66, 7-22, A-112
latches, high and low priority, 4-69
miscellaneous signals, 4-65
pin buffer example, 4-3, 4-10, 4-12
pin buffer, bidirectional, 4-13
rising and falling edge masks, 4-70
selection group B (data), 4-25
selection group C (frame sync), 4-31
selection group D (pin assignments),
4-36
selection group E (miscellaneous signals),
4-43 to 4-46
selection group F, 4-47
SRU1 connections for SPORTx, 4-14,
4-16
system configuration, sample, 4-76
system design, 4-3
DAI registers
core interrupt priority assignment
(DAI_IRPTL_PRI), 4-69
core interrupt priority assignment
register (DAI_IRPTL_PRI), 7-19,
A-114
DAI_IRPTL_FE register
as replacement to IMASK, 4-69
DAI_IRPTL_H register as replacement
to IRPTL, 4-69
DAI_IRPTL_L register as replacement
to IRPTL, 4-69
DAI registers (continued)
DAI_IRPTL_RE register as replacement
to IMASK register, 4-69
falling edge interrupt mask register
(DAI_IRPTL_FE), A-115
high priority interrupt
(DAI_IRPTL_H), A-113
high priority interrupt latch register
(DAI_IRPTL_H), 7-17, 7-28, A-114
interrupt falling edge (DAI_IRPTL_FE),
7-19, A-113
interrupt high priority
(DAI_IRPTL_H), A-114
interrupt rising edge (DAI_IRPTL_RE),
7-19, A-113
low priority interrupt (DAI_IRPTL_L),
A-113
low priority interrupt latch register
(DAI_IRPTL_L), 7-17, A-114
pin status (DAI_PIN_STAT), A-112,
A-116
ping-pong DMA status
(SRU_PINGx_STAT), A-110
resistor pull up enable
(DAI_PIN_PULLUP), A-111, A-115
resistor pullup enable
(DAI_PIN_PULLUP), A-111, A-115
rising edge interrupt mask register
(DAI_IRPTL_RE), A-115
shadow high priority interrupt latch
register (DAI_IRPTL_HS), A-114
shadow low priority interrupt latch
register (DAI_IRPTL_LS), A-114
status (DAI_STAT), 7-19, 7-25, 7-26,
A-109
data
alignment, external port, 3-25
buffers in DMA registers, 2-32
direction control (SPTRAN) bit, 5-64,
A-39