ADSP-21368 SHARC Processor Hardware Reference A-113
Register Reference
The DAI interrupt controller is configured using three registers. Each of
the 32 interrupt lines can be independently configured to trigger based on
the incoming signal’s rising edge, falling edge, both, or neither. Setting a
bit in
DAI_IRPTL_RE or DAI_IRPTL_FE enables that interrupt level on the
rising and falling edges, respectively.
The 32 interrupt signals within the DAI are mapped to two interrupt sig-
nals in the primary interrupt controller of the SHARC core. The
DAI_IRPTL_PRI register selects if the DAI interrupt is mapped to the high
priority or low priority core interrupt (1=high priority, 0 =low priority).
The DAI_IRPTL_H register is a read-only register that has bits set for every
DAI interrupt latched for the high priority core interrupt. The
DAI_IRPTL_L register is a read-only register that has bits set for every DAI
interrupt latched for the low priority core interrupt. When a DAI inter-
rupt occurs, the low or high priority core ISR queries its corresponding
register to determine which of the 32 interrupt sources requires service.
When DAI_IRPTL_H is read, the high priority latched interrupts are cleared.
When DAI_IRPTL_L is read, the low priority latched interrupts are cleared.
DMA overflow greater than N interrupts can be sensed only at rising
edges. Falling edges are not used for these ten interrupts (eight DMA, one
overflow, and one FIFO valid data greater than N).
The IDP_FIFO_GTN_INT interrupt is not cleared when the DAI_IRPTL_H/L
register is read. This gets cleared when cause of this interrupt is zero.
A read resets the value to 0, except under the following condition:
The IDP_FIFO_GTN_INT interrupt is not cleared when the DAI_IRPTL_H/L
registers are read. This register is cleared when the cause of this interrupt
is zero.
All of the DAI interrupt registers are used primarily to provide the status
of the resident interrupt controller. These registers are shown in
Figure A-44 described in Table A-46. Note that for each of these registers
the bit names and numbers are the same.
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