External Port Registers
A-22 ADSP-21368 SHARC Processor Hardware Reference
Figure A-9. SDRAM Control Register (Bits 0–15)
Table A-6. SDRAM Control Register Bit Descriptions
Bit Name Description
1–0 SDCL SDRAM CAS Latency. The delay in clock cycles between when
the SDRAM detects the read command and when it provides the
data at its output pins.
00, 01 = Reserved
10 = 2 cycles
11 = 3 cycles
2DSDCTLDisable SDCLK and Control Signals. Used to enable or disable
the SDC. If DSDCTL is disabled, any access to SDRAM address
space does not occur externally. When DSDCTL is disabled, all
SDC control pins are in their inactive states and the SDRAM
clock SDCLK is not running.
1 = Disable
0 = Activate
3 Reserved.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDCL
SDSRF
SDRAM Self Refresh Enable
1=Starts self refresh mode
0=No effect
SDPSS
SDRAM Power-up Sequence Start
1=Enable power-up on next
SDRAM access
0=No effect
DSDCTL
Disable SDCLK and Control Sig-
nals
1=Disable
0=Activate
CAS Latency
00, 01=Reserved
10=2 cycles, 11=3 cycles
Reserved
SDPM
SDRAM Power-Up Mode
1=Precharge, mode reg set, 8CBR refresh cycles
0=Precharge, 8CBR refresh cycles, mode reg set
SDCAW
SDRAM Bank Column Address Width
00=8 bits
01=9 bits
10=10 bits
11=11 bits
0000000000000000
SDTRAS
SDRAM tRAS Specification
Active command delay = 1–15
SDCLK cycles
SDTRP
SDRAM tRP Specification
Precharge delay = 1–7 SDCLK
cycles
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