SPI Data Transfer Operations
6-20 ADSP-21368 SHARC Processor Hardware Reference
Slave Transfer Preparation
When enabled as a slave, the device prepares for a new transfer according
to the function and actions described in Table 6-1.
The following steps illustrate the SPI receive or transmit DMA sequence
in an SPI slave in response to a master command:
1. Once the slave-select input is active, the processor starts receiving
and transmitting data on active
SPICLK edges. The data for one
channel (TX or RX) is automatically transferred from/to memory by
the IOP. The function of the other channel is dependant on the GM
and SENDZ bits in the SPICTL register.
2. Reception or transmission continues until the SPI DMA word
count register transitions from 1 to 0.
3. A number of conditions can occur while the processor is configured
for the slave mode:
• If the DMA engine cannot keep up with the receive data
stream during receive operations, the receive buffer operates
according to the state of the GM bit in the SPICTLx registers.
•If GM = 0 and the DMA buffer is full, the incoming data is
discarded and the RXSPIx register is not updated. While per-
forming a receive DMA, the transmit buffer is assumed to
be empty. If
SENDZ = 1, the device repeatedly transmits zeros
on the MISO pin. If SENDZ = 0, it repeatedly transmits the
contents of the TXSPIx registers.
•If
GM = 1 and the DMA buffer is full, the device continues to
receive new data from the
MOSI pin, overwriting the older
data in the DMA buffer.
• If the DMA engine cannot keep up with the transmit data
stream during a transmit operation because another DMA
engine has been granted the bus (or for another reason), the
To Next Page
Loading...
Need help?
General
