Serial Port Signals
5-6 ADSP-21368 SHARC Processor Hardware Reference
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Pairings of SPORTs (0 and 1, 2 and 3, and 4 and 5, 6 and 7) are
used only in loopback mode for testing.
A SPORT receives serial data on one of its bidirectional serial data signals
configured as inputs, or transmits serial data on the bidirectional serial
data signals configured as outputs. It can receive or transmit on both
channels simultaneously and unidirectionally, where the pair of data sig-
nals can both be configured as either transmitters or receivers.
The SPORTx_DA and SPORTx_DB channel data signals on each SPORT can-
not transmit and receive data simultaneously for full-duplex operation.
Two SPORTs must be combined to achieve full-duplex operation. The
SPTRAN bit in the SPCTLx register controls the direction for both the A and
B channel signals. Therefore, the direction of channel A and channel B on
a particular SPORT must be the same.
Serial communications are synchronized to a clock signal. Every data bit
must be accompanied by a clock pulse. Each SPORT can generate or
receive its own clock signal (SPORTx_CLK). Internally-generated serial clock
frequencies are configured in the DIVx registers. The A and B channel data
signals shift data based on the rate of SPORTx_CLK. See Figure 5-10 on
page 5-70 for more details.
In addition to the serial clock signal, data may be signaled by a frame syn-
chronization signal. The framing signal can occur at the beginning of an
individual word or at the beginning of a block of words. The configura-
tion of frame sync signals depends upon the type of serial device
connected to the processor. Each SPORT can generate or receive its own
frame sync signal (
SPORTx_FS) for transmitting or receiving data. Inter-
nally-generated frame sync frequencies are configured in the DIVx
registers. Both the A and B channel data signals shift data based on their
corresponding SPORTx_FS signal. See Figure 5-10 on page 5-70 for more
details.
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