Serial Peripheral Interface Registers
A-64 ADSP-21368 SHARC Processor Hardware Reference
SPI DMA Start Address Registers (IISPI, IISPIB)
The reset values for these registers are undefined. These 19-bit read-write
SPI registers contain the start address of the buffer in memory. Their
addresses are 0x1080 (for
IISPI) and 0x2880 (for IISPIB).
SPI DMA Address Modify Registers (IMSPI, IMSPIB)
The reset values for these registers are undefined. These 16-bit, read-write
SPI registers contain the address modifier. Their addresses are 0x1081 (for
IMSPI) and 0x2881 (for IMSPIB).
SPI DMA Word Count Registers (CSPI, CSPIB)
The reset values for these registers are undefined. These 16-bit, read-write
SPI registers contain the number of words to be transferred. Their
addresses are 0x1082 (for
CSPI) and 0x2882 (for CSPIB).
13–12 SPISx DMA FIFO Status.
00 = FIFO empty
11 = FIFO full
10 = FIFO partially full
01 = Reserved
14 SPIERRS DMA Error Status.
0 = Successful DMA transfer
1 = Errors during DMA transfer
15 SPIDMAS DMA Transfer Status.
0 = DMA idle
1 = DMA in progress
16 SPICHS DMA Chain Loading Status.
0 = Chain idle
1 = Chain loading in progress
31–17 Reserved
Table A-15. SPIDMAC, SPIDMACB Register Bit Descriptions (Cont’d)
Bit Name Description
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