Analog Devices SHARC ADSP-21368 - Page 685

ADSP-21368 SHARC Processor Hardware Reference A-37
Register Reference
Table A-8. SPCTLx Register Bit Descriptions
Bit Name Description
0SPEN_A Enable Channel A Serial Port.
0 = Serial port A channel disabled
1 = Serial port A channel enabled
This bit is reserved when the SPORT is in packed I
2
S and multichan-
nel modes.
2–1 DTYPE Data Type Select. Selects the data type formatting for normal and
multichannel transmissions as follows:
Normal Multichannel Data Type Formatting
00 x0 Right-justify, zero-fill unused MSBs
01 x1 Right-justify, sign-extend unused MSBs
10 0x Compand using μ-law
11 1x Compand using A-law
3LSBF Serial Word Endian Select.
0 = Big endian (MSB first)
1 = Little endian (LSB first)
This bit is reserved when the SPORT is in I
2
S or left-justified sample
pair modes.
8–4 SLEN Serial Word Length Select. Selects the word length in bits. For DSP
serial and multichannel modes, word sizes can be from 3 bits
(SLEN = 2) to 32 bits (SLEN = 31). For I
2
S and left-justified modes,
word sizes can be from 8 bits (SLEN = 7) to 32 bits (SLEN = 31).
9PACK 16-Bit to 32-Bit Word Packing Enable.
0 = Disable 16- to 32-bit word packing
1 = Enable 16- to 32-bit word packing
10 ICLK Internal Clock Select.
0 = Select external transmit clock
1 = Select the internal transmit clock
This bit applies to DSP serial and multichannel modes, including
packed I
2
S modes.
MSTR (I
2
S
mode only)
In I
2
S and left-justified sample pair mode, this bit selects the word
source and internal clock (if set, = 1) or external clock (if cleared, = 0)
11 OPMODE Sport Operation Mode.
0 = DSP serial/multichannel mode if cleared
1 = Selects the I
2
S, packed I
2
S, left-justified sample pair mode