Serial Port Registers
A-36 ADSP-21368 SHARC Processor Hardware Reference
Figure A-18. SPCTLx Register (Bits 15–0) for Packed I
2
S and
Multichannel Mode
15 14 13 12 11 10
9
876543210
0000000000000000
Reserved
Reserved
IMFS
DTYPE
Data Type
00=Right-justify, fill MSB with 0’s
01=Right-justify, sign-extend MSB
10=Compand υ-law
11=Compand A-law
LSBF
Serial Word Bit Order
1=LSB first
0=MSB first
SLEN
Serial Word Length-1
PACK
16/32 Packing
1=Packing
0=No packing
Internally Generated Multichannel
Frame Sync
1=Internal frame sync
0=External frame sync
OPMODE
SPORT Operation Mode
1=Packed I
2
S mode
0=Multichannel mode
CKRE
Active Clock Edge for Data and Frame
Sync Sampling
1=Rising edge
0=Falling edge
Reserved
ICLK
Internally Generated Clock
1=Internal clock
0=External clock
SPCTL0 (0xC00) SPCTL1 (0xC01)
SPCTL2 (0x400) SPCTL3 (0x401)
SPCTL4 (0x800) SPCTL5 (0x801)
SPCTL6 (0x4800) SPCTL7 (0x4801)
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