ADSP-21368 SHARC Processor Hardware Reference 2-31
I/O Processor
The following rules for data transfers must be followed.
• DMA addresses must always be normal word (32-bit) memory.
• Internal memory data transfer sizes are 32 bits, while external data
transfer sizes may be 32, 16, or 8 bits.
• The I/O processor can transfer short word data (16-bit) using the
packing capability of the serial port and SPI port DMA channels.
After transferring each data word to or from internal memory, the I/O
processor adds the modify value to the index register to generate the
address for the next DMA transfer and writes the modified index value to
the index register. The modify value in the modify register is a signed inte-
ger, which allows both increment and decrement modifies. The modify
value can have any positive or negative integer value. Note that:
• If the I/O processor modifies the index register past the maximum
18-bit value to indicate an address out of internal memory, the
index wraps around to zero. With the offset for the ADSP-2136x
SHARC processor processors, the wraparound address is
0x0008 0000.
• If a DMA channel is disabled, the I/O processor does not service
requests for that channel, (whether or not the channel has data to
transfer).
[
If a program loads the count register with zero, the I/O processor
does not disable DMA transfers on that channel. The I/O proces-
sor interprets the zero as a request for 2
16
transfers. This count
occurs because the I/O processor starts the first transfer before test-
ing the count value. The only way to disable a DMA channel is to
clear its DMA enable bit.
The processor’s 34 DMA channels are numbered as shown in Table 2-7.
This table also shows the control, parameter, and data buffer registers that
correspond to each channel.
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