ADSP-21368 SHARC Processor Hardware Reference 2-37
I/O Processor
3. If circular buffering is needed, then program additional writes to
the
ELEP and EBEP registers. Note that for normal chained DMA,
the ELEP and EBEP registers are not part of the TCB. So if circular
buffering is used with the normal chained DMA, all the DMA
blocks will have same ELEP and EBEP values.l
4. Enable DMA (DEN), chaining (CHEN), and circular buffering (CBEN)
if needed, in the DMACx registers. It is advised that the DMA FIFOs
are flushed (DFLSH) when DMA is enabled.
Once the DMA control register is initialized, the DMA controller fetches
the DMA descriptors from the address pointed to by the external port
chain pointer register (CPEP). The order the descriptors are fetched is
shown in Table 2-9.
The order the descriptors are fetched with circular buffering enabled is
shown in Table 2-10
Table 2-9. Chain Pointer Loading Sequence (Normal DMA)
Address Register Value
CPEP[18:0] IIEP
CPEP[18:0] – 0x1 IMEP
CPEP[18:0] – 0x2 ICEP
CPEP[18:0] – 0x3 EIEP
CPEP[18:0] – 0x4 EMEP
CPEP[18:0] – 0x5 CPEP
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