ADSP-21368 SHARC Processor Hardware Reference 2-15
I/O Processor
parameters stored in the processor’s internal memory. These are the
CPSPxy registers for the SPORTs, the CPEP register for the external port,
the RXCP_UACx registers for the UART, and the CPSPI register for the SPI.
Each new set of parameters is stored in a four-word, user-initialized buffer
in internal memory known as a transfer control block (TCB).
The structure of a TCB is conceptually the same as that of a traditional
linked list. Each TCB has several data values and a pointer to the next
TCB. Further, the chain pointer of a TCB may point to itself to con-
stantly reiterate the same DMA.
A DMA sequence is defined as the sum of the DMA transfers for a single
channel, from when the parameter registers initialize to when the count
register decrements to zero. Each DMA channel has a chaining enable bit
(CHEN) in the corresponding control register. This bit must be set to one to
enable chaining. When chaining is enabled, DMA transfers are initiated
by writing a memory address to the chain pointer register. This is also an
easy way to start a single DMA sequence, with no subsequent chained
DMAs.
The chain pointer register can be loaded at any time during the DMA
sequence. This allows a DMA channel to have chaining disabled (chain
pointer register address field = 0x0000) until some event occurs that loads
the chain pointer register with a nonzero value. Writing all zeros to the
address field of the chain pointer register also disables chaining.
If chaining is enabled on a DMA channel, programs should not use poll-
ing to determine channel status as it can provide inaccurate information.
In this case, the DMA appears inactive if it is sampled while the next
transfer control block (TCB) is loading.
L
Chained DMA operations may only occur within the same chan-
nel. The processor does not support cross-channel chaining.
The chain pointer register is 20 bits wide. The lower 19 bits are the mem-
ory address field. Like other I/O processor address registers, the chain
pointer register’s value is offset to match the starting address of the
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