SDRAM Controller
3-40 ADSP-21368 SHARC Processor Hardware Reference
SDRAM CAS latency parameter setting.
SDCL bits 1–0. The column
address strobe (CAS) latency is the delay in clock cycles between when the
SDRAM detects the read command and when it provides the data at its
output pins. Settings are: 10 = 2 cycles, 11 = 3 cycles.
Generally, the frequency of operation determines the value of the CAS
latency. For specific information about setting this value, consult the
SDRAM device documentation.
SDRAM controller disable. DSDCTL bit 2. Enables or disables the SDC. If
DSDCTL is set (=1), any access to SDRAM address space does not occur
externally. All SDC control pins are in their inactive states and the
SDRAM clock, SDCLK, does not run.
The DSDCTL bit is cleared (=0) by default, so that SDCLK is running after
reset deasserts. If the SDC is not used, the DSDCTL bit can be set to stop the
clock and reduce power dissipation. Even though the SDC is enabled at
reset, the power-up sequence must be executed before reading or writing
to SDRAM address space. Failure to execute the power-up sequence
before reading or writing to SDRAM address space results in unpredict-
able operation. However, DSDCTL must remain cleared at all times when
the SDC is needed to generate auto-refresh commands to the SDRAM.
SDRAM tRAS parameter setting. SDTRAS bits 7–4. The t
RAS
value (bank
activate command delay) defines the required delay, in number of SDCLK
cycles, between the time the SDC issues a bank activate command and the
time it issues a precharge command as shown below.
The SDRAM must also remain in self-refresh mode for a period of time of
at least t
RAS
. The t
RP
and t
RAS
values define the t
RFC
, t
RC
, and t
XSR
val-
ues. For more information, see “Timing External Memory Accesses” on
page 3-36.
SDTRAS
t
RASmin
t
SDCLK
--------------------
≥
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