ADSP-21368 SHARC Processor Hardware Reference 3-41
External Port
The t
RAS
parameter allows the ADSP-21367/8/9 and ADSP-2137x pro-
cessors to adapt to the timing requirements of the system’s SDRAM
devices. Any value between 1 and 15 SDCLK cycles can be selected as shown
in Table 3-14.
SDRAM tRP parameter setting. SDTRP bits 10–8. Defines the required
precharge delay, in number of SDCLK cycles, between the time the SDC
issues a precharge command and the time it issues a bank activate com-
mand as shown in the following equation.
The t
RP
setting also specifies the time required between precharge and
auto-refresh, and between precharge and self-refresh. Any value between 1
and 7
SDCLK cycles may be selected as shown in Table 3-15.
Table 3-14. Bank Activate Command Delay Bit Settings
Bit Setting Clock Cycles Bit Setting Clock Cycles
SDTRAS1 = 0000 Reserved SDTRAS8 = 1000 8
SDTRAS1 = 0001 1 SDTRAS9 = 1001 9
SDTRAS2 = 0010 2 SDTRAS10 = 1010 10
SDTRAS3 = 0011 3 SDTRAS11 = 1011 11
SDTRAS4 = 0100 4 SDTRAS12 = 1100 12
SDTRAS5 = 0101 5 SDTRAS13 = 1101 13
SDTRAS6 = 0110 6 SDTRAS14 = 1110 14
SDTRAS7 = 0111 7 SDTRAS15 = 1111 15
SDTRP
t
RPmin
t
SDCLK
------------------
≥
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