Analog Devices SHARC ADSP-21368 User Manual

SPI Data Transfer Operations
6-16 ADSP-21368 SHARC Processor Hardware Reference
4. For a single DMA, define the parameters of the DMA transfer by
writing to the
IISPIx, IMSPIx, and CSPIx registers. For DMA
chaining, also write the chain pointer address to the CPSPIx regis-
ters after the other DMA registers. For more information, see
“Setting Up and Starting Chained DMA over the SPI” on
page 2-42.
5. Write to the SPI DMA configuration registers, (SPIDMACx), to spec-
ify the DMA direction (SPIRCV, bit 1) and to enable the SPI DMA
engine (SPIDEN, bit 0). If DMA chaining is desired, set (= 1) the
SPICHEN bit (bit 4) in the SPIDMACx registers.
[
To avoid data corruption, enable the SPI port before enabling
DMA.
If flags are used as slave selects, programs should activate the flags by clear-
ing the flag after the SPICTLx and the SPIBAUDx registers are configured,
but before enabling the DMA. When CPHASE = 0, and a program is using
DMA, the flags are automatically activated by the SPI ports.
When enabled as a master, the DMA engine transmits or receives data as
follows:
1. If the SPI system is configured for transmitting, the DMA engine
reads data from memory into the SPI DMA FIFO. Data from the
DMA FIFO is loaded into the
TXSPIx registers and then into the
transmit shift register. This initiates the transfer on the SPI port.
2. If configured to receive, data from the
RXSPIx registers is automati-
cally loaded into the SPI DMA FIFO and the DMA engine reads
data from the SPI DMA FIFO and writes to memory. Finally, the
SPI initiates the receive transfer.

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP