ADSP-21368 SHARC Processor Hardware Reference 6-17
Serial Peripheral Interface Ports
3. The SPI generates the
SPICLK signal (as specified by CPHASE,
SPIBAUD, and other bit settings) and the data is shifted out of MOSI
and in from MISO simultaneously.
4. The SPI continues sending or receiving words until the SPI DMA
word count register decrements to 0.
If the DMA engine is unable to keep up with the transmit stream during a
transmit operation because the IOP requires the IOD (I/O data) bus to
service another DMA channel (or for another reason), the SPICLK signal
stalls until data is written into the TXSPI register. All aspects of SPI receive
operation should be ignored. The data in the RXSPI register is not
intended to be used, and the RXS (bits 28–27 and 31–30 in the SPCTLx reg-
isters) and SPISTAT bits (26 and 29) should be ignored. The ROVF overrun
condition cannot generate an error interrupt in this situation.
If the DMA engine cannot keep up with the receive data stream during
receive operations, then SPICLK stalls until data is read from RXSPI. While
performing a receive DMA, the processor core assumes the transmit buffer
is empty. If SENDZ = 1, the device repeatedly transmits zeros. If SENDZ = 0,
it repeatedly transmits the contents of the TXSPI register. The TUNF under-
run condition cannot generate an error interrupt in this situation.
L
For receive DMA in master mode, the SPICLK signal stops only
when the FIFO and the RXSPI buffer is full (even if the DMA
count is zero). Therefore, the
SPICLK signal runs for an additional
five word transfers filling junk data in the FIFO and the
RXSPIx
buffers. This data must be cleared before a new DMA is initiated.
A master SPI DMA sequence may involve back-to-back transmission
and/or reception of multiple chained DMA transfers. The SPI controller
supports such a sequence with minimal processor core interaction.
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