Shared Memory Interface
3-84 ADSP-21368 SHARC Processor Hardware Reference
and
MS3-0 are driven high (inactive) before three-stating occurs. The ACK
signal must be sampled high by the new master before it starts a new bus
operation. For more information, see Figure 3-16.
During bus transition cycle delays, execution of external accesses are
delayed. When one of the slave processors needs to perform an external
read or write, it automatically initiates the bus arbitration process by
asserting its BRx line. This read or write is delayed until the processor
receives bus mastership. If the read or write was generated by the proces-
sor’s core (not the I/O processor), program execution stops on that
processor until the instruction is completed.
The following steps occur as a slave acquires bus mastership and performs
an external read or write over the bus as shown in Figure 3-16.
1. The slave determines that it is executing an instruction which
requires an off-chip access. It asserts its BRx line at the beginning of
the cycle. Extra cycles are generated by the core processor (or I/O
processor) until the slave acquires bus mastership.
2. To acquire bus mastership, the slave waits for a bus transition cycle
in which the current bus master deasserts its BRx line. If the slave
has the highest priority request in the BTC, it becomes the bus
master in the next cycle. If not, it continues waiting.
3. At the end of the BTC, the current bus master releases the bus and
the new bus master starts driving.
During the CLKIN cycle in which the bus master deasserts its BRx output, it
three-states its outputs in case another bus master wins arbitration and
enables its drivers in the next
CLKIN cycle. If the current bus master retains
control of the bus in the next cycle, it enables its bus drivers, even if it has
no bus operation to run.
The processor with ID = 001 enables internal pull-up devices on key sig-
nals, including the address and data buses, strobes, and ACK. These devices
provide a weak current source or sink (approximate 20 kΩ impedance) to
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