I/O Processor Registers
A-8 ADSP-21368 SHARC Processor Hardware Reference
19 TMREXPEN Flag Timer Expired Mode.
0 = Flag3 pin is a general-purpose I/O pin. Permits core writes.
1 = Flag3 pin output is timer expired signal (TIMEXP).
20 MSEN Memory Select. Selects FLGx or MSx. Detailed modes of program-
ming for these bits are given in “Programming Flags” on page 14-9.
0=FLAG/IRQx
pins are selected
1=Enables FLAG2 and 3 (IRQ2 and TIMEXP) as MS2 and 3
23–21 EPDATA Data Pin Mode Select.
000 = DATA31–0 pins are data lines (default at RESET)
001 = DATA15–0 pins are data lines
010 = DATA7–0 pins are data lines
011 = DATA31–0 pins are FLAGS/PWM
100 = DATA31–8 pins are PDAP, DATA7–0 are data lines
101 = DATA31–8 pins are PDAP, DATA7–0 are flags
111 = Threestate DATA31–0 pins.
24 PWM0_3 Pulse Width Modulation Select.
When set (=1), enables DATA19–16 as PWM3–0.
25 PWM4_7 Pulse Width Modulation Select.
When set (=1), enables DATA23–20 as PWM7–4.
26 PWM8_11 Pulse Width Modulation Select.
When set (=1), enables DATA27–24 as PWM11–8.
27 PWM12_15 Pulse Width Modulation Select.
When set (=1), enables DATA31–28 as PWM15–12.
28 FSYNC Force Synchronization of the Shared Memory Bus.
0 = Do not force synchronization
1 = Force synchronization of the shared memory bus
29 BUSLK Bus Lock Request. Requests bus lock where the processor maintains
bus master control (if set, =1) or does not request bus lock (normal
bus master control) id cleared (=0).
31–30 Reserved
Table A-1. SYSCTL Register Bit Descriptions (Cont’d)
Bit Name Description
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