ADSP-21368 SHARC Processor Hardware Reference A-177
Register Reference
Table A-71. BRKCTL Register Bit Descriptions
Bit Name Description
1–0 PA1MODE PA1Triggering Mode.
00 = Breakpoint disabled
01 = WRITE access
10 = READ access
11 = Any access
3–2 DA1MODE DA1 Triggering Mode.
00 = Breakpoint disabled
01 = WRITE access
10 = READ access
11 = Any access
5–4 DA2MODE DA2 Triggering Mode.
00 = Breakpoint disabled
01 = WRITE access
10 = READ access
11 = Any access
7–6 IO1MODE IO1 Triggering Mode.
00 = Breakpoint is disabled
01 = WRITE accesses only
10 = READ accesses only
11 = Any access
9–8 EP1MODE EP1 Triggering Mode.
00 = Breakpoint disabled
01 = WRITE access
10 = READ access
11 = Any access
10 NEGPA1 Negate Program Memory Data Address Breakpoint.
Enable breakpoint events if the address is greater than the end
register value OR less than the start register value. This func-
tion is useful to detect index range violations in user code.
0 = Do not negate breakpoint
1 = Negate breakpoint
11 NEGDA1 Negate Data Memory Address Breakpoint #1.
For more information, see NEGPA1 bit description.
12 NEGDA2 Negate Data Memory Address Breakpoint #2.
For more information, see NEGPA1 bit description.