SDRAM Controller
3-38 ADSP-21368 SHARC Processor Hardware Reference
3. Enable the new divisors by setting the
DIVEN bit (bit 9 in the PMCTL
register). Do not set this bit at the same time as the PLLBP bit (bit
15 of the PMCTL register) is set. See “Power Management Control
Register” on page 14-14 for more information.
The new divisor ratios are picked up on the fly and the clocks
smoothly transition to their new values within 14 core clock (CCLK)
cycles.
The core clock frequency is:
CCLK = CLKIN × (PLL multiplier ÷ clock divider) where:
PLL multiplier = PLLM (1–64) and the PLL divider = 1, 2, 4 or 8.
The SDCLK frequency is SDCLK = CCLK ÷ SDRATIO.
If either the PLL divider or the
SDCLK to CCLK ratio (or both) are changed,
it may take up to 14
CCLK cycles for all the clocks to get the new value.
PLLD Bit Setting Clock Ratio
00 CCLK divider of 1
01 CCLK divider of 2
10 CCLK divider of 4
11 CCLK divider of 8
SDCKR Bit Setting Clock Ratio
000 SDCLK divider of 2
001 SDCLK divider of 2.5
010 SDCLK divider of 3
011 SDCLK divider of 3.5
100 SDCLK divider of 4
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