ADSP-21368 SHARC Processor Hardware Reference 3-59
External Port
The internal 32-bit non-multiplexed address is multiplexed into:
• SDRAM column address
• SDRAM row address
• Internal SDRAM bank address
The lowest bits are mapped into the column address, next bits are mapped
into the row address, and the final two bits are mapped into the internal
bank address. This mapping is based on the
SDCAW and SDRAW values pro-
grammed into the SDRAM control register.
The SDC uses no burst mode (BL = 1) for read and write operations. This
requires the SDC to post every read or write address on the bus as for
non-sequential reads or writes, but does not cause any performance degra-
dation. For ADSP-2137x processors, optional full page burst can be
activated, However, every single access is immediately interrupted by
another access resulting in no burst mode.
For read commands, there is a latency from the start of the read command
to the availability of data from the SDRAM, equal to the CAS latency.
This latency is always present for any single read transfer. Subsequent
reads do not have latency.
For more information on commands used by the SDRAM controller, see
“SDC Commands” on page 3-63.
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