I/O Mode
11-14 ADSP-21368 SHARC Processor Hardware Reference
Software can write up to two words into the
UARTxTHR register before
enabling the UART clock. As soon as the UART DMA engine is enabled,
those two words are sent.
Alternatively, UART writes and reads can be accomplished by interrupt
service routines (ISRs). Separate interrupt lines are provided for the trans-
mit, receive, and error signals. The independent interrupts can be enabled
individually by the UARTxIER register. In I/O mode, the receive interrupt is
generated for the following cases.
• When UARTxRBR is full
• On a receive overrun error
• On a receive parity error
• On a receive framing error
• On a break interrupt (RXSIN held low)
• When UARTxTHR is empty
• A transmit complete (UARTTXFI) interrupt
• An address detect (UARTADI) interrupt (for 9-bit mode)
The ISRs can evaluate the status bit field within the UART interrupt iden-
tification register (
UARTxIIR) to determine the signalling interrupt source.
If more than one source is signalling, the status field displays the one with
the highest priority. Interrupts also must be assigned and unmasked by the
processor’s interrupt controller. The ISRs must clear the interrupt latches
explicitly. See Figure A-54 on page A-125 and “Interrupt Priorities” on
page B-4.
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