ADSP-21368 SHARC Processor Hardware Reference 14-11
System Design
2. 32 data pins
• All 16 flags can be mapped.
• Can be mapped only in groups of four.
• Should be programmed through the
SYSCTL register. For
more information, see “System Control Register (SYSCTL)”
on page A-5.
3. 14 DPI pins
• 12 flags (FLAG4–15) can be mapped.
• Any flag can go to any DPI pins.
• Should be programmed through the SRU2 registers. For
more information, see “DPI/SRU2 Connection Groups” on
page 4-51.
The flag data paths from the processor core to the data pin multiplexer
block and SRU2 are parallel (Figure 14-1 on page 14-4). Therefore, for
FLAGS0–3:
• In output mode, if the same flag is mapped to both data pins and
flag pins, then the output comes from both pins.
• In input mode, if the same flag is mapped to both data pins and
flag pins, then the input from data pins is given priority.
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