ADSP-21368 SHARC Processor Hardware Reference A-163
Register Reference
3FSC_SOURCE_IOPEnable frame sync C input source.
0 = XTAL buffer output selected for frame sync C
1 = EXT_CLKA_I selected for frame sync C
16 FSD_SYNC Enable synchronization of frame sync D with external
frame sync.
0 = Frame sync disabled
1 = Frame sync enabled
17 CLKD_SYNC Enable synchronization of clock D with external frame
sync.
0 = Clock disabled
1 = Clock enabled
18 CLKD_SOURCE_IOP Enable clock D input source.
0 = XTAL buffer output selected for clock D
1 = EXT_CLKA_I selected for clock D
19 FSD_SOURCE_IOP Enable frame sync D input source.
0 = XTAL buffer output selected for frame sync D
1 = EXT_CLKA_I selected for frame sync D
Table A-68. PCG_SYNC2 Register Bit Descriptions (Cont’d)
Bit Name Description
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