Analog Devices SHARC ADSP-21368

Setting Up DMA Parameter Registers
2-34 ADSP-21368 SHARC Processor Hardware Reference
23 IDP_CTL IDP_DMA_I7,
IDP_DMA_M7,
IDP_DMA_C7
IDP_FIFO DAI IDP
Channel 7
24 SPICTL IISPI, IMSPI, CSPI, CPSPI RXSPI, TXSPI SPI Data
25 SPICTLB IISPIB, IMSPIB, CSPIB,
CPSPIB
RXSPIB,
TXSPIB
SPI B Data
26 MTMCTL IIMTMW
IMMTMW,
CMTMW
N/A MTM Write
Channel
27 MTMCTL IIMTMR,
IMMTMR,
CMTMR
N/A MTM Read
Channel
28 AMICTL EIEP0, EMEP0, ECEP0,
IIEP0, IMEP0, ICEP0,
CEP0, CPEP0, EBEP0,
TPEP0, ELEP0
DFEP0, TFEP0External
Port
Channel 0
29 AMICTL EIEP1, EMEP1, ECEP1,
IIEP1, IMEP1, ICEP1,
CEP1, CPEP1, EBEP1,
TPEP1, ELEP1
DFEP1, TFEP1External
Port
Channel 1
30 RXCTL_UAC0 RXI_UAC0, RXM_UAC0,
RXC_UAC0, RXCP_UAC0,
RXSTAT_UAC0
RBR0,
RBRSH_UAC0
UART0 Rx
31 RXCTL_UAC1 RXI_UAC1, RXM_UAC1,
RXC_UAC1, RXCP_UAC1,
RXSTAT_UAC1
RBR1,
RBRSH_UAC1
UART1 Rx
Table 2-7. DMA Channel Registers: Controls, Parameters,
and Buffers (Cont’d)
DMA
Channel
Number
Control Registers Parameter Registers Buffer Registers Description