Analog Devices SHARC ADSP-21368 - Page 610

Clock Derivation
14-18 ADSP-21368 SHARC Processor Hardware Reference
Listing 14-4. PLL Programming Example 2
ustat2 = dm(PMCTL);
bit clr ustat2 PLLM63|PLLD8; /* clear old multiplier and
divisor*/
bit set ustat2 PLLBP | PLLD4 |PLLM16; /* set a multiplier of 16
and a divider of 4 and
enable Bypass mode*/
ustat2 = dm(PMCTL);
waiting_loop:
r0 = 4096; /* wait for PLL to lock at new rate
(requirement for modifying multiplier only) */
lcntr = r0, do pllwait until lce;
pllwait: nop;ustat2 = dm(PMCTL);
bit clr ustat2 PLLBP; /* take PLL out of Bypass*/
dm(PMCTL) = ustat2;
ustat2 = dm(PMCTL);
bit set ustat2 DIVEN; /* Enable the DIVEN bit, PLL is now at
CLKIN*4 (CoreCLK = CLKIN * M/N = CLKIN* 16/4) */
dm(PMCTL) = ustat2;
Listing 14-5 is a PLL programming example in C.
Listing 14-5. PLL Programming Sequence (C)
pmctlsetting= *pPMCTL;
pmctlsetting &= ~(0xFF); /* Clear */
/* CLKIN= 24.576 MHz, Multiplier= 27, Divisor= 2,
CCLK_SDCLK_RATIO 2. */