ADSP-21368 SHARC Processor Hardware Reference 14-17
System Design
dm(PMCTL) = ustat2;
waiting_loop:
r0 = 4096; /* wait for PLL to lock at new rate
(requirement for modifying
multiplier only) */
lcntr = r0, do pllwait until lce;
pllwait: nop;
ustat2 = dm(PMCTL);
bit clr ustat2 PLLBP; /* take PLL out of Bypass, PLL is now at
CLKIN*4 (CoreCLK = CLKIN * M/N =
CLKIN* 16/4) */
dm(PMCTL) = ustat2;
Use the following alternate procedure to program the PLL.
1. Set the PLL multiplier and divisor values and place the PLL in
bypass mode by setting the PLLBP bit.
2. Wait in the bypass mode until the PLL locks.
3. Take the PLL out of bypass mode by clearing the bypass bit.
4. Wait for one core clock cycle.
5. Enable the divisor by setting the DIVEN bit.
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