ADSP-21368 SHARC Processor Hardware Reference 9-23
S/PDIF Transmitter/Receiver
audio sample and slowly and linearly decrementing it to zero, over a
period of 4096 frames. During this time, the PLL three-states the charge
pump until the soft mute has been completed. If non-linear PCM audio
data is in the AES3/SPDIF stream when the
NOSTREAM bit is asserted, the
receiver sends out zeros after the last valid sample.
When the DIR_LOCK bit is deasserted, it means that the PLL has become
unlocked and the audio data is handled according to the
DIR_NOAUDIO[1:0] bits in the DIRCTL register. When this happens, the
receiver functions as follows.
• 00 = no action is taken with the audio data.
• 01 = the last valid audio sample is held.
• 10 = zeros are sent out after the last valid sample.
• 11 = soft mute of the last valid audio sample is performed (as if
DIR_NOSTREAM is asserted).
This is valid only when linear PCM audio data is in the stream.
When non-linear audio data is in the stream, this mode defaults to
the case of DIR_NOAUDIO[1:0] bits = 10.
When a parity or bi-phase error occurs, the audio data is handled accord-
ing to the DIR_BIPHASEERROR_CTL[1:0] bits in the following manner.
• 00 = no action is taken with the audio data.
• 01 = the last valid sample is held.
• 10 = the invalid sample is replaced with zeros.
The
VALIDITY, NONAUDIO, NOSTREAM, BIPHERR, PARITY and LOCK bits are also
stored in the receiver status register as W1C bits.
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