Moving Data Between SPORTs and Internal Memory
5-74 ADSP-21368 SHARC Processor Hardware Reference
Data-direction programmability is supported in standard DSP standard
serial, left-justified sample pair, and I
2
S modes. The value of the SPTRAN
bit in SPCTLx (0 = RX, 1 = TX) determines whether the receive or transmit
register for the SPORT becomes active.
The SPORT DMA channels are assigned higher priority than all other
DMA channels (for example, the SPI port) because of their relatively low
service rate and their inability to hold off incoming data. Having a higher
priority causes the SPORT DMA transfers to perform first when multiple
DMA requests occur in the same cycle.
Table 5-11. Serial Port DMA Channels
Channel Data Buffer Description Priority
0 RXSP1A/TXSP1A SPORT1 A data Highest
1 RXSP1B/TXSP1B SPORT1 B data
2 RXSP0A/TXSP0A SPORT0 A data
3 RXSP0B/TXSP0B SPORT0 B data
4 RXSP3A/TXSP3A SPORT3 A data
5 RXSP3B/TXSP3B SPORT3 B data
6 RXSP2A/TXSP2A SPORT2 A data
7 RXSP2B/TXSP2B SPORT2 B data
8 RXSP5A/TXSP5A SPORT5 A data
9 RXSP5B/TXSP5B SPORT5 B data
10 RXSP4A/TXSP4A SPORT4 A data
11 RXSP4B/TXSP4B SPORT4 B data
12 RXSP7A/TXSP7A SPORT7 A data
13 RXSP7B/TXSP7B SPORT7 B data
14 RXSP6A/TXSP6A SPORT6 A data
15 RXSP6B/TXSP6B SPORT6 B data Lowest
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