Error Signals and Flags
6-36 ADSP-21368 SHARC Processor Hardware Reference
The SPI ports are able to respond appropriately to this situation. To
enable this feature, set the
ISSEN bit in the SPICTL register. As soon as this
error is detected, the following actions are taken:
1. The SPIMS control bit in SPICTL is cleared, configuring the SPI
interface as a slave.
2. The SPIEN control bit in SPICTL is cleared, disabling the SPI
system.
3. The MME status bit in SPISTAT is set.
4. An SPI interrupt is generated.
These four conditions persist until the MME bit is cleared by a write
1-to-clear (W1C-type) software operation. Until the MME bit is cleared, the
SPI cannot be re-enabled, even as a slave. Hardware prevents the program
from setting either SPIEN or SPIMS while MME is set.
When MME is cleared, the interrupt is deactivated. Before attempting to
re-enable the SPI as a master, the state of the SPIDS input pin should be
checked to ensure that it is high; otherwise, once SPIEN and SPIMS are set,
another mode-fault error condition occurs immediately. The state of the
input pin is reflected in the input slave-select status bit (bit 7) in the SPI-
FLG
register.
L
As a result of SPIEN and SPIMS being cleared, the SPI data and clock
pin drivers (
MOSI, MISO, and SPICLK) are disabled. However, the
slave-select output pins revert to control by the processor flag I/O
module registers. This may cause contention on the slave-select
lines if these lines are still being driven by the processor. In order to
ensure that the slave-select output drivers are disabled once a MME
error occurs, the program must configure these pins as inputs by
setting (= 1) the flag output select bits,
FLAG3–0O, in the FLAGS reg-
ister prior to configuring the SPI port. See the FLAGs value
register description in the ADSP-2136x SHARC Processor Program-
ming Reference “Registers” Appendix.
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