Precision Clock Generator Registers
A-156 ADSP-21368 SHARC Processor Hardware Reference
Figure A-73. PCG_CTLx0 Registers
Table A-63. PCG_CTLx0 Register Bit Descriptions
Bit Name Description
19–0 FSxDIV Divisor for Frame Sync A/B/C/D.
29–20 FSxPHASE_HI Phase for Frame Sync A/B/C/D.
This field represents the upper half of the 20-bit value for the
channel A/B/C/D frame sync phase.
See also FSXPHASE_LO (Bits 29-20) in PCG_CTLX_1
described on page A-157.
30 ENFSx Enable Frame Sync A/B/C/D.
0 = Specified frame sync generation disabled
1 = Specified frame sync generation enabled
31 ENCLKx Enable Clock A/B/C/D.
0 = Specified clock generation disabled
1 = Specified clock generation enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
ENCLKA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Enable Clock A/B/C/D
Frame Sync A/B/C/D Divisor
FSADIV
Frame Sync A/B/C/D Phase
FSAPHASE_HI
ENFSA
Enable Frame Sync A/B/C/D
PCG_CTLA0 (0x24C0)
PCG_CTLB0 (0x24C2)
PCG_CTLC0 (0x24C6)
PCG_CTLD0 (0x24C8)
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