ADSP-21368 SHARC Processor Hardware Reference 5-83
Serial Ports
The third listing, Listing 5-3, transmits a buffer of data from
SPORT1 to
SPORT0 using DMA chaining and the internal loopback feature of the
SPORT. In this example, SPORT5 drives the clock and frame sync, and the
two TCBs for each SPORT are set up to ping-pong back and forth to con-
tinually send and receive data.
Listing 5-1. SPORT Transmit Using DMA Chaining
/* SPORT DMA Parameter Registers */
#define IISP4A 0x840
#define IISP5A 0x848
#define IMSP4A 0x841
#define IMSP5A 0x849
#define CSP4A 0x842
#define CSP5A 0x84A
/* SPORT Control Registers */
#define DIV4 0x802
#define DIV5 0x803
#define SPCTL4 0x800
#define SPCTL5 0x801
#define SPMCTL4 0x804
/* SPMCTL Bits */
#define SPL 0x00001000
/* SPCTL Bits */
#define SPEN_A 0x00000001
#define SDEN_A 0x00040000
#define SLEN32 0x000001F0
#define SPTRAN 0x02000000
#define IFS 0x00004000
#define FSR 0x00002000
#define ICLK 0x00000400
To Next Page
Loading...
Need help?
General
