Analog Devices SHARC ADSP-21368 - Page 369

ADSP-21368 SHARC Processor Hardware Reference 5-89
Serial Ports
Listing 5-3. SPORT Transmit Using DMA
/* SPORT DMA Parameter Registers */
#define CPSP0A 0xC43
#define CPSP1A 0xC4B
/* SPORT Control Registers */
#define DIV0 0xC02
#define DIV1 0xC03
#define SPCTL0 0xC00
#define SPCTL1 0xC01
#define SPMCTL0 0xC04
/* SPMCTL Bits */
#define SPL 0x00001000
/* SPCTL Bits */
#define SPEN_A 0x00000001
#define SDEN_A 0x00040000
#define SCHEN_A 0x00080000
#define SLEN32 0x000001F0
#define SPTRAN 0x02000000
#define IFS 0x00004000
#define FSR 0x00002000
#define ICLK 0x00000400
/* Default Buffer Length */
#define BUFSIZE 10
.SECTION/DM seg_dmda;
/* TX Buffers */
.var tx_buf1a[BUFSIZE] = 0x11111111,
0x22222222,
0x33333333,